{"id":838,"date":"2019-09-17T19:14:17","date_gmt":"2019-09-17T19:14:17","guid":{"rendered":"http:\/\/panda.dei.polimi.it\/?page_id=838"},"modified":"2021-02-15T11:06:49","modified_gmt":"2021-02-15T11:06:49","slug":"pact-2019-tutorial","status":"publish","type":"page","link":"https:\/\/panda.deib.polimi.it\/?page_id=838","title":{"rendered":"PACT-2019 tutorial"},"content":{"rendered":"\r\n<h2 class=\"wp-block-heading\">Bambu: Productive FPGA Programming for Complex Parallel Applications<\/h2>\r\n\r\n\r\n\r\n<p>PACT19 &#8211; The 28th International Conference on Parallel Architectures and Compilation Techniques<br>\r\nSeattle, WA, USA<\/p>\r\n\r\n\r\n\r\n<p>September 21<sup>st<\/sup>, Saturday, 8:00am-5:00pm<\/p>\r\n\r\n\r\n\r\n<p><\/p>\r\n\r\n\r\n\r\n<h4 class=\"wp-block-heading\" id=\"organizers\">Organizers:<\/h4>\r\n\r\n\r\n\r\n<p>Fabrizio Ferrandi (Politecnico di Milano), Vito Giovanni Castellana  (PNNL), Marco Minutoli (PNNL), Marco Lattuada (Politecnico di Milano),  Antonino Tumeo (PNNL)<\/p>\r\n\r\n\r\n\r\n<h4 class=\"wp-block-heading\" id=\"location\">Location:<\/h4>\r\n\r\n\r\n\r\n<p>Room: Seattle Ballroom 3<\/p>\r\n\r\n\r\n\r\n<h4 class=\"wp-block-heading\">Abstract<\/h4>\r\n\r\n\r\n\r\n<p style=\"text-align:left\">Accelerators implemented on reconfigurable hardware and, in particular, on Field Programmable Gate Arrays (FPGAs), are experiencing renewed interest in High-Performance Computing. The possibility to finely customize the design of the accelerators to the applications can provide benefits in terms of efficiency with respect to fixed accelerators, especially for data-intensive applications. FPGAs have traditionally been programmed with hardware description languages, requiring significant engineering efforts and long development times. Today, the availability of new tools to generate accelerators starting from high-level (parallel) specifications provides easier access to FPGAs and preserves programmer productivity.<\/p>\r\n\r\n\r\n\r\n<p>This tutorial will discuss the impact of FPGAs for HPC, focusing on applications from the areas of data analytics and machine learning. The tutorial will dive into approaches for the High-Level Synthesis (HLS) of parallel applications, highlighting key methodologies, trends, advantages, benefits, but also gaps that still need to be closed. The tutorial will provide a hands-on experience of Bambu, one of the most advanced HLS tools available. Able to support the majority of C constructs, Bambu integrates with many logic <g class=\"gr_ gr_40 gr-alert gr_gramm gr_inline_cards gr_run_anim Grammar multiReplace\" id=\"40\" data-gr-id=\"40\">synthesis<\/g> and simulations tools, generating accelerators for a variety of FPGA vendors, starting from parallel code annotated with OpenMP. It also optimizes the memory architectures of the generated accelerators.<\/p>\r\n\r\n\r\n\r\n<h5 class=\"wp-block-heading\">Tutorial material<\/h5>\r\n\r\n\r\n\r\n<p>The slide of the tutorial are the following:<\/p>\r\n\r\n\r\n\r\n<ul class=\"wp-block-list\"><li>Presentation of <g class=\"gr_ gr_7 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del multiReplace\" id=\"7\" data-gr-id=\"7\">bambu<\/g> [<a href=\"https:\/\/github.com\/ferrandi\/PandA-bambu\/raw\/main\/documentation\/tutorial_pact_2019\/Introduction\/Introduction.pdf\">PDF<\/a>]<\/li><li>Exploiting Vectorization in High-Level Synthesis of Nested Irregular Loops [<a href=\"https:\/\/github.com\/ferrandi\/PandA-bambu\/raw\/main\/documentation\/tutorial_pact_2019\/SIMD\/Simd.pdf\">PDF<\/a>]<\/li><li>Compiler Based Optimizations, Tuning and Customization of Generated Accelerators [<a href=\"https:\/\/github.com\/ferrandi\/PandA-bambu\/raw\/main\/documentation\/tutorial_pact_2019\/Optimization\/Optimizations.pdf\">PDF<\/a>]<\/li><li>Target Customization and Tool Integration [<a href=\"https:\/\/github.com\/ferrandi\/PandA-bambu\/raw\/main\/documentation\/tutorial_pact_2019\/Target-Customization\/Target-Customization.pdf\">PDF<\/a>]<\/li><li>Enabling the High-Level Synthesis of Data Analytics Accelerators [<a href=\"https:\/\/github.com\/ferrandi\/PandA-bambu\/raw\/main\/documentation\/tutorial_pact_2019\/Context-Switch\/Context-Switch.pdf\">PDF<\/a>]<\/li><\/ul>\r\n\r\n\r\n\r\n<h5 class=\"wp-block-heading\">Virtual machine<\/h5>\r\n\r\n\r\n\r\n<p>You can download a VirtualBox virtual machine with a pre-configured \r\nversion of Bambu. The machine requires about 8GB of free space on your \r\ndisk. (Username: ubuntu \u2014 Password: password).<\/p>\r\n\r\n\r\n\r\n<p>The two files are shared through Dropbox facility and they require just a recent version of VirtualBox software.<\/p>\r\n\r\n\r\n\r\n<p><a href=\"https:\/\/www.dropbox.com\/s\/gzfuby6a80wwaki\/PandA-bambu-VM_32bit.ova?dl=0\">VirtualBox virtual machine with a pre-configured version of Bambu running on Ubuntu-desktop 16.04 LTS 32bits<br><\/a><a href=\"https:\/\/www.dropbox.com\/s\/256u4r18xvlo5k0\/PandA-bambu-VM_64bit.ova?dl=0\">VirtualBox virtual machine with a pre-configured version of Bambu running on Ubuntu-desktop 18.04 LTS 64bits<\/a><br><\/p>\r\n\r\n\r\n\r\n<h5 class=\"wp-block-heading\">Organizers and Short Bios<\/h5>\r\n\r\n\r\n\r\n<p><em><strong>Fabrizio Ferrandi, Associate Professor, Politecnico di Milano, Italy<\/strong><\/em><br> Fabrizio Ferrandi received his Laurea (cum laude) in Electronic  Engineering in 1992 and the Ph.D. degree in Information and Automation  Engineering (Computer Engineering) from the Politecnico di Milano,  Italy, in 1997. He joined the faculty of Politecnico di Milano in 1999  as \u201cRicercatore\u201d and later in 2002 as Associate Professor with the  Dipartimento di Elettronica, Informazione e Bioingegneria. His research interests include synthesis, verification simulation and testing of digital circuits and systems. He published more than 150 papers in international journals, conference and book chapters. Fabrizio Ferrandi is a member of the IEEE Computer Society since 1995, the Test Technology  Technical Committee, and the European Design and Automation  Association.<\/p>\r\n\r\n\r\n\r\n<p><strong><em>Vito Giovanni Castellana, Senior Research Scientist, Pacific Northwest National Laboratory, United States of America<\/em><\/strong><br>Dr. Vito Giovanni Castellana received the M.S degree in Informatic Engineering, in 2010, and the Ph.D. degree in Computer Engineering, in 2014, from Politecnico di Milano in  Italy. Since February 2014, he has been a research scientist in the  PNNL&#8217;s High-Performance Computing group. He joined PNNL in 2012 as a <g class=\"gr_ gr_159 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del multiReplace\" id=\"159\" data-gr-id=\"159\">post master<\/g> research associate. His research interests are embedded systems and computer architectures, design automation, and, <g class=\"gr_ gr_167 gr-alert gr_gramm gr_inline_cards gr_run_anim Style multiReplace\" id=\"167\" data-gr-id=\"167\">HPC .<\/g> <\/p>\r\n\r\n\r\n\r\n<p><strong><em>Marco Minutoli, Research Scientist, Pacific Northwest National Laboratory, United States of America<\/em><\/strong><br>Marco Minutoli received the M.S degree in Informatic Engineering, in 2014 from Politecnico di Milano in  Italy. Since February 2016, he has been a research scientist in the  PNNL&#8217;s High-Performance Computing group. He joined PNNL in 2014 as a post <g class=\"gr_ gr_9 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del multiReplace gr-progress sel\" id=\"9\" data-gr-id=\"9\">m<\/g>aster research associate. Since 2016 is a Ph.D. candidate in Computer Science at Washington State University. His research interests are focused on the design and analysis of data structures and graph algorithms for high performance and big data applications. <\/p>\r\n\r\n\r\n\r\n<p><em><strong>Marco Lattuada, Postdoctoral Researcher, Politecnico di Milano, Italy<\/strong><\/em><br> Marco Lattuada received the Master and the Ph.D. degrees in Computer  Engineering from Politecnico di Milano, Italy, in 2006 and 2010,  respectively. In 2012 and 2013 he was visiting researcher at European  Space Agency. Since 2010, he has been temporary researcher and lecturer at Dipartimento di Elettronica, Informazione e Bioingegneria of  Politecnico di Milano. His research interests include methodologies for embedded system design and in particular high-level synthesis,  performance estimation and automatic code generation for multiprocessor heterogeneous architectures. He has actively participated in several projects sponsored by <g class=\"gr_ gr_9 gr-alert gr_gramm gr_inline_cards gr_run_anim Grammar only-ins replaceWithoutSep\" id=\"9\" data-gr-id=\"9\">European<\/g> Union and by <g class=\"gr_ gr_10 gr-alert gr_gramm gr_inline_cards gr_run_anim Grammar only-ins replaceWithoutSep\" id=\"10\" data-gr-id=\"10\">European<\/g> Space Agency. He is a Member of the Association for Computing Machinery.<\/p>\r\n\r\n\r\n\r\n<p><strong><em>Antonino Tumeo, Senior Research Scientist, Pacific Northwest National Laboratory, United States of America<\/em><\/strong><br>Dr. Antonino Tumeo received the M.S degree in Informatic Engineering, in 2005, and the Ph.D. degree in Computer Engineering, in 2009, from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in the PNNL&#8217;s High-Performance Computing group. He joined PNNL in 2009 as a <g class=\"gr_ gr_24 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del multiReplace\" id=\"24\" data-gr-id=\"24\">post doctoral<\/g> research associate. Previously, he was a post<g class=\"gr_ gr_22 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del\" id=\"22\" data-gr-id=\"22\">&#8211;<\/g>doctoral researcher at Politecnico di Milano. His research interests are modeling and simulation of high-performance architectures, hardware-software codesign, FPGA prototyping and GPGPU computing. <\/p>\r\n","protected":false},"excerpt":{"rendered":"<p>Bambu: Productive FPGA Programming for Complex Parallel Applications PACT19 &#8211; The 28th International Conference on Parallel Architectures and Compilation Techniques Seattle, WA, USA September 21st, Saturday, 8:00am-5:00pm Organizers: Fabrizio Ferrandi (Politecnico di Milano), Vito Giovanni Castellana (PNNL), Marco Minutoli (PNNL), Marco Lattuada (Politecnico di Milano), Antonino Tumeo (PNNL) Location: Room: Seattle Ballroom 3 Abstract Accelerators &hellip; <a href=\"https:\/\/panda.deib.polimi.it\/?page_id=838\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">PACT-2019 tutorial<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":649,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-838","page","type-page","status-publish","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>PACT-2019 tutorial - panda.deib.polimi.it<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/panda.deib.polimi.it\/?page_id=838\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"PACT-2019 tutorial - panda.deib.polimi.it\" \/>\n<meta property=\"og:description\" content=\"Bambu: Productive FPGA Programming for Complex Parallel Applications PACT19 &#8211; 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