Bambu: Productive FPGA Programming for Complex Parallel Applications

PACT19 – The 28th International Conference on Parallel Architectures and Compilation Techniques
Seattle, WA, USA

September 21^st, Saturday, 8:00am-5:00pm

Organizers:

Fabrizio Ferrandi (Politecnico di Milano), Vito Giovanni Castellana (PNNL), Marco Minutoli (PNNL), Marco Lattuada (Politecnico di Milano), Antonino Tumeo (PNNL)

Location:

Room: Seattle Ballroom 3

Abstract

Accelerators implemented on reconfigurable hardware and, in particular, on Field Programmable Gate Arrays (FPGAs), are experiencing renewed interest in High-Performance Computing. The possibility to finely customize the design of the accelerators to the applications can provide benefits in terms of efficiency with respect to fixed accelerators, especially for data-intensive applications. FPGAs have traditionally been programmed with hardware description languages, requiring significant engineering efforts and long development times. Today, the availability of new tools to generate accelerators starting from high-level (parallel) specifications provides easier access to FPGAs and preserves programmer productivity.

This tutorial will discuss the impact of FPGAs for HPC, focusing on applications from the areas of data analytics and machine learning. The tutorial will dive into approaches for the High-Level Synthesis (HLS) of parallel applications, highlighting key methodologies, trends, advantages, benefits, but also gaps that still need to be closed. The tutorial will provide a hands-on experience of Bambu, one of the most advanced HLS tools available. Able to support the majority of C constructs, Bambu integrates with many logic synthesis and simulations tools, generating accelerators for a variety of FPGA vendors, starting from parallel code annotated with OpenMP. It also optimizes the memory architectures of the generated accelerators.

Tutorial material

The slide of the tutorial are the following:

• Presentation of bambu [PDF]
• Exploiting Vectorization in High-Level Synthesis of Nested Irregular Loops [PDF]
• Compiler Based Optimizations, Tuning and Customization of Generated Accelerators [PDF]
• Target Customization and Tool Integration [PDF]
• Enabling the High-Level Synthesis of Data Analytics Accelerators [PDF]

Virtual machine

You can download a VirtualBox virtual machine with a pre-configured version of Bambu. The machine requires about 8GB of free space on your disk. (Username: ubuntu — Password: password).

The two files are shared through Dropbox facility and they require just a recent version of VirtualBox software.

VirtualBox virtual machine with a pre-configured version of Bambu running on Ubuntu-desktop 16.04 LTS 32bits
VirtualBox virtual machine with a pre-configured version of Bambu running on Ubuntu-desktop 18.04 LTS 64bits

Organizers and Short Bios

Fabrizio Ferrandi, Associate Professor, Politecnico di Milano, Italy
Fabrizio Ferrandi received his Laurea (cum laude) in Electronic Engineering in 1992 and the Ph.D. degree in Information and Automation Engineering (Computer Engineering) from the Politecnico di Milano, Italy, in 1997. He joined the faculty of Politecnico di Milano in 1999 as “Ricercatore” and later in 2002 as Associate Professor with the Dipartimento di Elettronica, Informazione e Bioingegneria. His research interests include synthesis, verification simulation and testing of digital circuits and systems. He published more than 150 papers in international journals, conference and book chapters. Fabrizio Ferrandi is a member of the IEEE Computer Society since 1995, the Test Technology Technical Committee, and the European Design and Automation Association.

Vito Giovanni Castellana, Senior Research Scientist, Pacific Northwest National Laboratory, United States of America
Dr. Vito Giovanni Castellana received the M.S degree in Informatic Engineering, in 2010, and the Ph.D. degree in Computer Engineering, in 2014, from Politecnico di Milano in Italy. Since February 2014, he has been a research scientist in the PNNL’s High-Performance Computing group. He joined PNNL in 2012 as a post master research associate. His research interests are embedded systems and computer architectures, design automation, and, HPC .

Marco Minutoli, Research Scientist, Pacific Northwest National Laboratory, United States of America
Marco Minutoli received the M.S degree in Informatic Engineering, in 2014 from Politecnico di Milano in Italy. Since February 2016, he has been a research scientist in the PNNL’s High-Performance Computing group. He joined PNNL in 2014 as a post master research associate. Since 2016 is a Ph.D. candidate in Computer Science at Washington State University. His research interests are focused on the design and analysis of data structures and graph algorithms for high performance and big data applications.

Marco Lattuada, Postdoctoral Researcher, Politecnico di Milano, Italy
Marco Lattuada received the Master and the Ph.D. degrees in Computer Engineering from Politecnico di Milano, Italy, in 2006 and 2010, respectively. In 2012 and 2013 he was visiting researcher at European Space Agency. Since 2010, he has been temporary researcher and lecturer at Dipartimento di Elettronica, Informazione e Bioingegneria of Politecnico di Milano. His research interests include methodologies for embedded system design and in particular high-level synthesis, performance estimation and automatic code generation for multiprocessor heterogeneous architectures. He has actively participated in several projects sponsored by European Union and by European Space Agency. He is a Member of the Association for Computing Machinery.

Antonino Tumeo, Senior Research Scientist, Pacific Northwest National Laboratory, United States of America
Dr. Antonino Tumeo received the M.S degree in Informatic Engineering, in 2005, and the Ph.D. degree in Computer Engineering, in 2009, from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in the PNNL’s High-Performance Computing group. He joined PNNL in 2009 as a post doctoral research associate. Previously, he was a post–doctoral researcher at Politecnico di Milano. His research interests are modeling and simulation of high-performance architectures, hardware-software codesign, FPGA prototyping and GPGPU computing.